The invention relates to a method of locking in a phase-locked loop (PLL) around a YIG-tuned oscillator whose frequency is guided into the PLL capture range by a frequency-control loop provided with a frequency discriminator, with the frequency-control loop being able to be switched off after the PLL has locked in; The invention additionally relates to an arrangement for executing the method.
YIG-tuned oscillators are used to suppress the phase jitter near a platform, usually by means of a PLL coupled to a quartz oscillator that is frequency stable in the long term. When a change occurs in the frequency, the small capture range of the relatively narrow-bandwidth PLL is problematic with respect to locking into a new operating frequency.
It is known (Floyd M. Gardner, Phaselock Techniques, Wiley & Sons, New York, 1979, pp. 84-87) to support the lock-in of the PLL with an additional frequency-control loop. In the frequency-control loop, a frequency discriminator is used to determine the control deviation. As soon as the frequency of the YIG-tuned oscillator is guided into the PLL capture range by means of the frequency-control loop, the YIG-tuned oscillator is almost exclusively controlled by the frequency-control loop. If desired, the frequency-control loop can then be shut off (Gardner; see above). YIG-tuned oscillators can be subject to aging, and have a hysteresis, which has a negative effect on the precision of the control of the oscillator frequency via the primary-coil current of the YIG-tuned oscillator. This control is necessary when a change occurs in the frequency for returning the oscillator frequency to the capture range of the control loops.
It is an object of the invention to provide a lock-in method for a YIG-tuned oscillator that takes into consideration aging and hysteresis of the YIG-tuned oscillator. It is a further object of the invention to provide an arrangement for executing the method.